1. The Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More particularly, the present invention is directed to methods of selectively etching a material from an opening in a structural layer of a semiconductor wafer with a preference for more rapidly etching the material from an upper portion of the opening than from a lower portion of the opening. The method of the present invention is particularly useful in removing cusps from the surface of a contact opening with a high aspect ratio in order that the contact opening can be filled with uniform step coverage.
2. The Relevant Technology
Recent advances in computer technology and in electronics in general have been brought about at least in part as a result of the progress that has been achieved by the integrated circuit industry in electronic circuit densification and miniaturization. This progress has resulted in increasingly compact and efficient semiconductor devices, attended by an increase in the complexity and number of semiconductor devices aggregated on a single integrated circuit wafer. The smaller and more complex semiconductor devices, including resistors, capacitors, diodes, and transistors, have been achieved, in part, by reducing semiconductor device sizes and spacing and by reducing the junction depth of active regions formed on a silicon substrate of an integrated circuit wafer. The smaller and more complex semiconductor devices have also been achieved by stacking the semiconductor devices at various levels on the wafer.
Among the semiconductor device features which are being reduced in size are the electrical communication interconnect structures through which electrical contact is made between discrete semiconductor devices, or portions of such devices, located on nonadjacent levels of the wafer. These electrical communication interconnect structures include contacts, vias, plugs, trenches, and other structures, whereby electrical connection is made to discrete semiconductor devices, or components of semiconductor devices, located at the varying levels of integrated circuit wafers. These and other such interconnect structures will hereafter be collectively referred to as "interconnect structures." Interconnect structure openings are defined herein as etched conduits between layers which, when filled with conductive material, form the interconnect structure. By way of example, a contact opening is an interconnect structure opening that is filled with a conductive material to form an interconnect structure called a contact. In order to continue in the process of reducing integrated circuit size, new interconnect structure formation methods which overcome certain problems existing in the art are required.
Many of the problems currently encountered when forming interconnect structures arise from the fact that the interconnect structure openings are becoming increasingly smaller. Interconnect structure openings are currently designed with diameters within the half micron range. Also, the aspect ratio of the interconnect structure openings, the ratio of the height of the openings in which interconnect structures are formed to the width of these openings, is becoming very high. Aspect ratios for contact openings are currently greater than about three. It is difficult to deposit with good step coverage the necessary conducting filler material in these tiny, narrow, high sided contact openings. These factors make it difficult to form increasingly miniaturized interconnect structures which retain a high conductivity.
Currently, interconnect structure openings are filled with conducting filler material using one of two processes, chemical vapor deposition (CVD) and physical vapor deposition (PVD), the latter of which is also known as sputtering. Each of these processes has limitations and associated problems. For instance, limitations of the materials that can be deposited with CVD make it impractical for many applications. A shortcoming of existing PVD processes involves the phenomena of cusping, which occurs as a result of nonuniform step coverage, when high aspect ratio interconnect structure openings are being filled. Cusping also occurs to a lesser degree in CVD processes.
The problem of cusping will be discussed herein in greater detail in conjunction with the contact structure of FIG. 1. A specific type of contact known as a tungsten plug is being formed therein. Typically in the formation of a tungsten plug, an active region 12 on a silicon substrate 10 is being connected with surface metallization layers. A contact opening 14 is formed through a passivation layer 15, and a diffusion barrier liner layer 16 is deposited over contact opening 14. Diffusion barrier liner layer 16 is typically formed of titanium, which has a high tendency to form cusps 18 at a surface 13 of contact opening 14. Cusps 18 are formed by the deposition of large quantities of the conducting filler material concentrated at a the top of contact opening 14. Rather than being deposited in the bottom of contact opening 14, the slight angularity of the trajectory of sputtered material causes the fill material to aggregate at a mouth at the top of contact opening mouth 14, resulting in cusps 18.
Cusps 18 grow during continued deposition, progressively blocking the top or mouth of contact opening 14 until contact opening 14 is finally pinched off. Consequently, during the subsequent step of filling the remainder of contact opening 14 with a tungsten 18 layer 22, as shown in FIG. 2, tungsten layer 22 will close over cusps 14 and pinch off the top of contact opening 14, leaving a keyhole 19. The presence of a keyhole in a contact opening causes a high contact resistance, a reduction in semiconductor device speed, and a potential failure of the semiconductor device, particularly as the aspect ratio of the contact opening increases.
Attempts to remedy the angularity of the trajectory of sputtered material which causes cusping have included the use of collimators. Collimators are honeycombed structures used within PVD chambers to block the deposition of sputtered materials impinging at angles to the wafer. Nevertheless, collimators only reduce the degree of cusping, and cannot fully prevent it.
Thus, it becomes apparent that in order to continue in the progress of integrated circuit densification and miniaturization, an improved method is needed which reduces or eliminates cusping in the formation of interconnect structures. Such a method would be particularly beneficial if a contact could be formed thereby with a high aspect ratio and a high conductivity.